DS21Q58L【PDF 22/74 页】IC TXRX E1 QUAD 3.3V 100-LQFP

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Sheet目录1994

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DS21Q58 E1 Quad Transceiver

29 of 74

SSR

Synchronizer Status Register

09 Hex

Bit #

Name

CSC5

CSC4

CSC3

CSC2

CSC0

FASSA

CASSA

CRC4SA

NAME

BIT

FUNCTION

CSC5

CRC4 Sync Counter Bit 5. MSB of the 6-bit counter.

CSC4

CRC4 Sync Counter Bit 4

CSC3

CRC4 Sync Counter Bit 3

CSC2

CRC4 Sync Counter Bit 2

CSC0

CRC4 Sync Counter Bit 0. LSB of the 6-bit counter. Counter bit 1 is not

accessible.

FASSA

FAS Sync Active. Set while the synchronizer is searching for alignment at the

FAS level.

CASSA

CAS MF Sync Active. Set while the synchronizer is searching for the CAS MF

alignment word.

CRC4SA

CRC4 MF Sync Active. Set while the synchronizer is searching for the CRC4

MF alignment word.

9.2 CRC4 Sync Counter

The CRC4 sync counter increments each time the 8ms CRC4 multiframe search times out. The counter is cleared

when the framer has successfully obtained synchronization at the CRC4 level. The counter can also be cleared by

disabling the CRC4 mode (CCR1.0 = 0). This counter is useful for determining the amount of time the framer has

been searching for synchronization at the CRC4 level. ITU G.706 suggests that if synchronization at the CRC4

level cannot be obtained within 400ms, the search should be abandoned and proper action taken. The CRC4 sync

counter rolls over.

Table 9-1. Alarm Criteria

ALARM

SET CRITERIA

CLEAR CRITERIA

ITU SPEC

RSA1

(Receive Signaling

All Ones)

Over 16 consecutive frames (one full

MF) time slot 16 contains less than three

zeros

Over 16 consecutive frames (one full

MF) time slot 16 contains three or more

zeros

G.732

4.2

RSA0

(Receive Signaling

All Zeros)

Over 16 consecutive frames (one full

MF) time slot 16 contains all zeros

Over 16 consecutive frames (one full

MF) time slot 16 contains at least a

single one

G.732

5.2

RDMA

(Receive Distant

Multiframe Alarm)

Bit 6 in time slot 16 of frame 0 set to one

for two consecutive MF

Bit 6 in time slot 16 of frame 0 set to

zero for two consecutive MF

O.162

2.1.5

RUA1

(Receive Unframed

All Ones)

Fewer than three zeros in two frames

(512 bits)

More than two zeros in two frames (512

bits)

O.162

1.6.1.2

RRA

(Receive Remote

Alarm)

Bit 3 of nonalign frame set to one for

three consecutive occasions

Bit 3 of nonalign frame set to zero for

three consecutive occasions

O.162

2.1.4

RCL

(Receive Carrier

Loss)

255 (or 2048) consecutive zeros

received

In 255-bit times at least 32 ones are

received

G.775/

G.962

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